As is known, phase-change memories (or PCMs) are a new generation of non-volatile memories wherein, in order to store information, the characteristics of materials having the property of switching between phases with different electrical characteristics are exploited. These materials are able to switch between a disordered/amorphous phase and an ordered crystalline or polycrystalline phase. Different phases are characterized by different resistivity values and are associated with various values of a stored data. For example, the elements of group VI of the periodic table, such as tellurium (Te), selenium (Se) or antimony (Sb), also known as chalcogenides or chalcogenic materials, may be used for manufacturing phase-change memory cells; in particular, an alloy formed from germanium (Ge), antimony (Sb) and tellurium (Te), known as GST (having the chemical composition Ge2Sb2Te5), is currently widely used in such memory cells.
The changes of phase may be obtained by locally increasing the temperature of the cells of chalcogenic material, using resistive electrodes (generally known as heaters) placed in contact with corresponding regions of chalcogenic material.
Access (or selection) devices (for example, MOSFET transistors) are connected to the heaters and selectively allow the passage of a modify electric current through them; by Joule effect, this electric current generates the temperature required for the change of phase.
In particular, when the chalcogenic material is in the amorphous state, and thus has a high resistivity (RESET state), it is necessary to apply a current/voltage pulse (or a suitable number of current/voltage pulses) having a duration and an amplitude such as to allow the chalcogenic material to cool down slowly. When subjected to this treatment, the chalcogenic material changes its state and switches from the high-resistivity state to a low-resistivity state (SET state). Vice versa, when the chalcogenic material is in the SET state, it is necessary to apply a current/voltage pulse having a suitable duration and a high amplitude, to cause the chalcogenic material to return into the amorphous RESET state with high resistivity.
During reading, the state of the chalcogenic material is detected by applying a sufficiently low voltage as not to cause a substantial heating, and then by reading the value of the current flowing in the memory cell through a sense amplifier. Since the current is proportional to the conductivity of the chalcogenic material, it is possible to determine the state of the material, and as a consequence to determine the datum stored in the memory cell.
Analogously to other memory types, in phase-change memories, the memory device has decoding stages that, depending on address signals supplied by a control unit, allow access to single memory cells or specific groups of memory cells, supplying the preset voltages and detecting the sought electrical characteristics.
In particular, phase-change memories have separate column decoding stages for reading and modify phases. In fact, as explained above, these phases require significantly different voltage (and current) levels to be applied. As a consequence, the column decoding stages are optimized with respect to the appropriate operational phase and are only active during either phase.
This causes difficulties when it is desired to directly access single memory cells, for example in case of the mode referred to as direct memory access (DMA). In particular, such a mode allows the reading/modify circuits normally used during the operation of the memory to be bypassed, for example in order to verify the functionality of some parts of the memory and/or in order to verify operational margins of the cells. In fact, the possibility of directly accessing the cells allows to distinguish whether a given reading error is due to a failure of the relevant memory cell or to a problem on the addressing path or in the downstream circuits. Furthermore, DMA allows to evaluate whether the cell reading value, even if correct, is due to operation of the cell in a marginal region of the range of acceptable value, and thus it does not ensure a correct operation under various operating conditions of the cell, for example at different temperatures and/or as a result of aging.
It follows that the DMA accessing mode turns out to be useful in various situations, starting from the final electrical test phase (e.g., Electrical Wafer Sorting or EWS).
In memories of different type, for example in flash memories, the DMA access is simplified the presence of charge pumps capable of generating the voltages needed in the provided paths.
However, such a solution is not applicable to PCM memories, in which charge pumps are not present and the addressing paths of the cells are separate. In fact, in the reading paths, devices (N-channel transistors) are present that only operate at low voltages (for example, lower than 0.8 V) that are off at higher voltages or even, in some situations, may be damaged by higher voltages. On the other hand, in the modify paths, devices (P-channel transistors) are present that only operate at high voltages (for example, higher than 0.8 V) that are off at lower voltages.